1. Field of the Invention
The present invention is generally related to the field of semiconductor processing, and, more particularly, to a method for planarizing semiconductor wafers.
2. Description of the Related Art
Chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) is widely used as a means of planarizing various process layers, e.g., silicon dioxide, formed above a wafer comprised of a semiconducting material, such as silicon. Chemical mechanical polishing operations typically employ an abrasive slurry distributed in an alkaline or acidic solution to planarize the surface of a process layer through the combination of mechanical and chemical actions.
FIG. 1 is a schematic drawing of one illustrative embodiment of a chemical mechanical polishing tool used in semiconductor processing operations. As depicted therein, the illustrative polishing tool 10 is comprised of a rotatable table 12 on which a polishing pad 14 is mounted, and a multi-head carrier 16 positioned above the pad 14. The multi-head carrier 16 includes a plurality of rotatable polishing arms 18, each of which includes a carrier head 20. Typically, wafers are secured to the carrier heads 18 by the use of vacuum pressure. This is sometimes referred to as the carrier backforce pressure. In use, the table 12 is rotated and an abrasive slurry is dispersed onto the polishing pad 14. Once the slurry has been applied to the polishing pad 14, a downforce is applied to each rotating polishing arm 18 to press its respective wafer against the polishing pad 14. As the wafer is pressed against the polishing pad 14, the surface of the wafer is mechanically and chemically polished. Although the device depicted in FIG. 1 is a multi-head polishing device, similar single-head type machines exist in the industry, and the present invention is not limited to any particular embodiment, form or structure of a tool that may be used to perform chemical mechanical polishing operations.
As known to those in the industry, there has been, and continues to be, a constant drive to reduce the various feature sizes of semiconductor devices, e.g., transistors, used in modem electronic devices. The continual drive to reduce the various feature sizes arises, in part, by the desire for devices that operate at faster and faster speeds. That is, all other things being equal, the smaller the channel length of a transistor, the faster the transistor will operate. This continual drive to reduce feature sizes on semiconductor devices has increased the importance of chemical mechanical polishing or planarization in the semiconductor fabrication process. For example, as feature sizes tend to decrease, the depth of field of photolithography equipment tends to shrink, thereby necessitating a very flat surface in order that very small dimensions may be accurately patterned on a wafer.
One problem encountered with known methods for performing CMP processes is that such methods fail to account for variations in the thickness of a process layer to be polished. For example, a particular process specification for a particular device may provide that a process layer comprised of, for example, silicon dioxide, is to be formed to a design thickness of 2000 xc3x85. However, the thickness of the process layer after it is actually formed may vary from the design thickness, i.e., the thickness of the process layer may range between 1900 and 2100 xc3x85 due to inherent problems in forming such layers using existing semiconductor fabrication processes and equipment. In such situations, polishing recipes, e.g., the process parameters used to control polishing operations, such as the time duration of the polishing operation, the downforce applied by the polishing arm, etc., selected based upon the design thickness, e.g., 2000 xc3x85, of the process layer, may be inadequate to compensate for the variations in the thickness of the process layer as actually formed. That is, in the case where the process layer is thicker than the design thickness, the standard process recipe would not remove enough of the process layer. Conversely, in situations where the process layer is formed to a thickness that is less than the design thickness, the standard process recipe may remove more of the layer than is desired.
The end result of all of these variations is that the thickness of a process layer on the wafer after it has been subjected to standard polishing operations deviates from what is anticipated by the design process. If the thickness of the process layer after polishing is less or greater than the desired thickness of the process layer after polishing, problems can occur. After polishing operations, wafers are typically subjected to photolithography and etching processes to define various structures or features in the process layer.
For example, after patterning a layer of a photoresist, the wafer may be subjected to one or more etching processes to define a plurality of gate conductors in a layer of polysilicon. In performing these etching operations, the wafer may be subjected to etching processes that are designed based upon the anticipated thickness of the process layer after polishing. If the process layer, after polishing, is less than the anticipated thickness, then the etching recipe may, in fact, over-etch the process layer which may lead to damage of the underlying surface. In the alternative case, if the process layer, after polishing, is thicker than the anticipated thickness of the process layer, the etching process based upon the anticipated thickness may be inadequate to remove all of the process layer. In the case of an interlayer dielectric layer, e.g., silicon dioxide, performing a standard polishing, operation on a process layer that is thinner than anticipated may lead to short circuits in the semiconductor device, or other types of problems.
Additionally, due to such problems, the wafer may need to be subjected to further processing operations, e.g., additional polishing or etching time, to compensate for the over-thickness of the process layer. All of these problems tend to increase the cost and time of semiconductor fabrication and may adversely impact device performance.
The present invention is directed to a method of solving, or at least reducing, some or all of the aforementioned problems.
The present invention is directed to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of the process layer.